As technology advances, layouts must be designed to meet scaling requirements, for instance, based on the decreasing size of technology nodes, creating significant process integration risks for the middle-of-line (MOL) processes. For example, to satisfy scaling requirements, designers typically utilize constructs such as diffusion contact flyovers (CA flyovers), for instance, to implement cross-coupling-based designs. However, as technology nodes continue to scale down, the use of CA flyovers increases the risk that transistors and other integrated structures are unintentionally activated, reducing the integrity of the overall device. Moreover, as technology nodes scale down, costs associated with masks are significantly increased for MOL processes (e.g., diffusion contacts, metal1 layer structures, etc.). Furthermore, the number of masks for MOL processes may increase under traditional techniques, driving costs even higher. By way of example, traditional techniques may require triple patterning to form diffusion contacts and metal1 layer structures that satisfy tip-to-tip space requirements of diffusion contacts (e.g., in the power rail region) and metal1 layer structures for 14 nm technology nodes and beyond.
A need therefore exists for layout designs with alternative routing structures to CA flyover (such as via routing structures) along with such designs implemented using self-aligned double patterning (SADP) processes, and enabling methodology.